DC-DC converter with substantially constant on-time and constant switching frequency

ABSTRACT

A comparator-system DC-DC converter  1  according to an embodiment of the present invention comprises a control unit  200  which has a comparator section  20, 40  which compares the output voltage of the voltage conversion section with a reference voltage and determines a predetermined ON width of the ON pulse of the control signal Ssw or a predetermined OFF width of the OFF pulse of the control signal Ssw, and frequency control means  25  which compares the control signal Ssw with reference clock Cref and adjusts the ON width or OFF width so that the frequency of the control signal Ssw is constant. The frequency control means  25  detects a state where the output current of the voltage conversion section  100  is 0 A or a state where the output current is going to be 0 A and stops the processing to adjust the ON width or OFF width.

TECHNICAL FIELD

The present invention relates to a comparator-system DC-DC converter.

BACKGROUND ART

DC-DC converters which generate an output voltage that is stabilized byan input voltage are known. A variety of systems have been proposed asmeans for stabilizing the output voltage of a DC-DC converter. Forexample, Patent Document 1 mentions a switching DC-DC converter whichuses a PWM (pulse width modulation) system. With the PWM system, theoutput voltage can be stabilized by fixing the switching frequency andadjusting the ON pulse width. There are also switching DC-DC converterswhich employ a comparator system. With a comparator system, the outputvoltage can be stabilized by using the comparator to fix the ON pulsewidth and adjust the OFF pulse width (that is, the switching frequency).

This DC-DC converter is sometimes used as the power source of a PU(Processor Unit) or the like. When the PU moves from a standby state toa processing state, the current consumption increases suddenly. When theoutput voltage suddenly drops as a result of a sudden increase in theload current, the comparator-system DC-DC converter immediately outputsan ON pulse and, therefore, in comparison with a PWM system which isincapable of outputting a pulse in a predetermined OFF pulse period, theoutput voltage stabilizes rapidly. Thus, in comparison with a PWMsystem, a comparator-system DC-DC converter may have the characteristicof a favorable response characteristic with respect to a sudden increasein the load current.

[Patent Document 1] Japanese Patent Application Laid-Open No.2000-287439

DISCLOSURE OF INVENTION Problem to be Solved by the Invention

Furthermore, in a comparator-system DC-DC converter, the switching cycleTf is Tf=Pon+Poff=Vout/Vin×Tf+((Vin−Vout)/Vin)×Tf . . . (Equation (1))where the ON pulse width is Pon, the OFF pulse width is Poff, the inputvoltage is Vin, and the output voltage is Vout. Therefore, in caseswhere Vin and Vout are fixed, the ON pulse width Pon is constant andPoff is therefore fixed uniquely. In other words, with thecomparator-system DC-DC converter, because the Pon is constant, if Vinand Vout are fixed, the ON duty for making the output voltage constantis fixed.

Here, for example, when the ambient temperature rises, the internalresistance of the circuit element increases and the internal lossincreases. Here, with the comparator-system DC-DC converter, the OFFpulse width grows short and the ON duty increases in order to compensatefor the drop in the output voltage due to the increase in the internalloss. Thus, with the comparator-system DC-DC converter, the switchingfrequency gradually fluctuates due to the fluctuations in the ambienttemperature. Otherwise, the OFF pulse width also fluctuates and theswitching frequency fluctuates due to fluctuations in the input voltage,output voltage, and output current. Due to fluctuations in the switchingfrequency, the ripple of the output voltage fluctuates and there is thepossibility of a downstream circuit such as the PU operatingerroneously. There is also the possibility of EMI countermeasuresextending over a wide bandwidth being required.

However, although the switching frequency can be constant for aPWM-system DC-DC converter, in discontinuous mode, which has a periodduring which the load current is small and the output current is equalto or less than 0 A, the ON pulse width is sometimes excessively narrow.As a result, the possibility of a disturbance of the switching waveformexists. Circuit elements require a high speed characteristic.

Therefore, an object of the present invention is to provide acomparator-system DC-DC converter which is capable of reducingfluctuations in the switching frequency without impairing the responsecharacteristic with respect to a sudden increase in the load current ina continuous load current mode and which is capable of suppressing anexcessively narrow ON pulse width in the discontinuous load currentmode.

Means for Solving the Problem

The comparator-system DC-DC converter of the present invention comprisesa voltage conversion section which has an input terminal to which aninput voltage is input and a pair of output terminals, and further has aswitching element having one current terminal connected to the inputterminal, an inductor having one end connected to the other currentterminal of the switching element and another end connected to one ofthe pair of output terminals, and a smoothing capacitor connectedbetween the pair of output terminals, the voltage conversion sectiongenerating an output voltage which is obtained by voltage-converting theinput voltage, across the pair of output terminals by controlling theswitching element in accordance with a control signal which is a pulsesignal; and a control unit which generates the control signal forstabilizing the output voltage of the voltage conversion section. Thecontrol unit comprises a comparator section which compares the outputvoltage of the voltage conversion section with a reference voltage anddetermines a predetermined ON width of an ON pulse of the control signalor a predetermined OFF width of the OFF pulse of the control signal inaccordance with the comparison result; and frequency control means whichcompares the control signal with a reference clock and adjusts thepredetermined ON width of the ON pulse or the predetermined OFF width ofthe OFF pulse in accordance with the comparison result so that therepetition frequency of the control signal is constant. The frequencycontrol means comprises an adjustment stoppage section which detects astate where an output current which flows in a direction from theswitching element of the voltage conversion section toward the inductoris 0 A or a state where the output current is going to be 0 A andgenerates an adjustment stoppage signal which stops the processing ofthe frequency control means to adjust the predetermined ON width or thepredetermined OFF width.

With the comparator-system DC-DC converter, in continuous load currentmode, a predetermined ON width of the ON pulse (predetermined OFF widthof the OFF pulse) is also adjusted by frequency control means in caseswhere the OFF width of the OFF pulse has narrowed as a result of anincrease in the output current, for example (in cases where the ON widthof the ON pulse has widened) and the frequency of the control signal iskept fixed. Therefore, in the continuous load current mode, fluctuationsin the switching frequency can be reduced.

Here, the frequency control means keep the frequency of the controlsignal constant by adjusting the predetermined ON width of the ON pulse(predetermined OFF width of the OFF pulse). Hence, the ON width of theON pulse is sometimes excessively narrow in the discontinuous loadcurrent mode as is the case with the PWM system.

However, with this comparator-system DC-DC converter, because theprocessing to adjust the predetermined ON width of the ON pulse (thepredetermined OFF width of the OFF pulse) is stopped by the frequencycontrol means in cases where the output current is 0 A or is going to be0 A in the discontinuous load current mode, a narrowing of the ON widthof the ON pulse is suppressed. Hence, in the discontinuous load currentmode, a substantial narrowing of the ON width of the ON pulse can besuppressed.

The comparator section preferably comprises a first comparator whichdetects that the output voltage of the voltage conversion section issmaller than the reference voltage and determines the detection timepoint as the start time point of the ON pulse (OFF pulse); and a secondcomparator which detects that a predetermined time has elapsed since thestart time point of the ON pulse (OFF pulse) and determines thedetection time point as the end time point of the ON pulse (OFF pulse),and wherein the frequency control means preferably comprises anadjustment section which adjusts the predetermined ON width (thepredetermined OFF width) by adjusting the predetermined time.

The frequency control means preferably comprises a reference clockgeneration section which generates the reference clock; and in caseswhere the frequency control means acquires the adjustment stoppagesignal from the adjustment stoppage section, the reference clockgeneration section preferably temporarily stops the generation of thereference clock and stops the processing to adjust the predetermined ONwidth or the predetermined OFF width.

With a constitution of this kind, because the generation of thereference clock is temporarily stopped by the reference clock generationmeans in cases where the adjustment stoppage signal is acquired from theadjustment stoppage section, changes in the results of the comparisonbetween the control signal and reference clock by the frequency controlmeans can be stopped. The processing to adjust the predetermined ONwidth or the predetermined OFF width performed by the frequency controlmeans can therefore be stopped.

Furthermore, in cases where the frequency control means acquires theadjustment stoppage signal from the adjustment stoppage section, thefrequency control means may stop the comparison between the controlsignal and the reference clock and stop the processing to adjust thepredetermined ON width or the predetermined OFF width.

With a constitution of this kind, because the comparison between thecontrol signal and reference clock is stopped by the frequency controlmeans in cases where the adjustment stoppage signal is acquired from theadjustment stoppage section, changes in the result of the comparisonbetween the control signal and reference clock can be stopped. Hence,the processing to adjust the predetermined ON width or predetermined OFFwidth performed by the frequency control means can be stopped.

In addition, in cases where the adjustment stoppage signal is acquiredfrom the adjustment stoppage section, the frequency control means maystop the processing to adjust the predetermined ON width or thepredetermined OFF width by substituting the result of comparing thecontrol signal with the reference clock, with a predetermined fixedvalue which is determined beforehand.

With a constitution of this kind, because the result of comparing thecontrol signal with the reference clock is substituted with apredetermined fixed value which is determined beforehand by thefrequency control means in cases where the adjustment stoppage signal isacquired from the adjustment stoppage section, the processing to adjustthe predetermined ON width or the predetermined OFF width can bestopped.

EFFECTS OF THE INVENTION

The present invention makes it possible to obtain a comparator-systemDC-DC converter which is capable of reducing fluctuations in theswitching frequency without impairing the response characteristic withrespect to a sudden increase in the load current in a continuous loadcurrent mode and which is able to suppress an excessively narrow ONpulse width in the discontinuous load current mode.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a circuit diagram which shows a comparator-system DC-DCconverter according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram which shows a timer section of FIG. 1.

FIG. 3 shows a circuit diagram which shows an adjustment section of FIG.1.

FIG. 4 is a circuit diagram which shows an adjustment stoppage sectionof FIG. 1.

FIG. 5 is a circuit diagram which shows a reference clock generationsection of FIG. 1.

FIG. 6 is a timing chart which shows the respective signal waveforms ofthe continuous current mode of the comparator-system DC-DC convertershown in FIG. 1.

FIG. 7 is a timing chart which shows the respective signal waveforms ofthe continuous current mode of the adjustment section shown in FIG. 3.

FIG. 8 is a timing chart which shows the respective signal waveforms ofthe discontinuous current mode of the comparator-system DC-DC convertershown in FIG. 1.

FIG. 9 is a timing chart which shows the respective signal waveforms ofthe discontinuous current mode of the reference clock generation sectionshown in FIG. 5.

FIG. 10 is a timing chart which shows the respective signal waveforms ofthe discontinuous current mode of the adjustment section shown in FIG.3.

FIG. 11 shows the switching frequency characteristic with respect to theload current of the comparator-system DC-DC converter shown in FIG. 1.

FIG. 12 is a circuit diagram which shows a comparator-system DC-DCconverter according to a second embodiment of the present invention.

FIG. 13 is a circuit diagram which shows an adjustment stoppage sectionshown in FIG. 12.

FIG. 14 is a circuit diagram which shows a comparator-system DC-DCconverter according to a third embodiment of the present invention.

FIG. 15 is a circuit diagram which shows an adjustment section shown inFIG. 14.

FIG. 16 is a timing chart which shows the respective signal waveforms inthe discontinuous current mode of the adjustment section shown in FIG.15.

FIG. 17 is a circuit diagram which shows a comparator-system DC-DCconverter according to a fourth embodiment of the present invention.

FIG. 18 is a circuit diagram which shows an adjustment stoppage sectionwhich is shown in FIG. 17.

FIG. 19 is a circuit diagram which shows an adjustment section which isshown in FIG. 17.

FIG. 20 is a timing chart which shows the respective signal waveforms ofthe discontinuous current mode of the adjustment stoppage section whichis shown in FIG. 18.

FIG. 21 is a circuit diagram which shows an adjustment section accordingto a modified example 1.

FIG. 22 is a circuit diagram which shows an adjustment section accordingto a modified example 2.

FIG. 23 shows a current detection method according to a modifiedexample.

FIG. 24 is a circuit diagram which shows a reference clock generationsection according to a modified example.

FIG. 25 is a respective part signal waveform of a reference clockgeneration section according to a modified example.

LIST OF ELEMENTS

-   -   1 comparator-system DC-DC converter    -   2 input terminal    -   3 output terminal    -   11 switching element    -   12 diode    -   13 drive circuit    -   14 inductor    -   15 smoothing capacitor    -   16, 17 resistance element    -   18 capacitor    -   20 first comparator (comparator section)    -   25 frequency control means    -   30 timer section    -   31 fixed current generation circuit (fixed current source)    -   32 timer capacitor    -   33 transistor    -   34 input voltage division circuit    -   35 voltage follower    -   36 resistance element    -   37 current mirror circuit    -   38 gm amplifier    -   40 second comparator (comparator section)    -   60 adjustment section    -   61 first counter    -   62 second counter    -   68 up/down counter    -   70 adjustment stoppage section    -   71 detected voltage division circuit    -   72 comparator    -   75 delay reset signal generation section    -   80 reference clock generation section    -   100 voltage conversion section    -   200 control unit

BEST MODE FOR CARRYING OUT THE INVENTION

Preferred embodiments of the present invention will be described indetail hereinbelow with reference to the drawings. The same referencenumerals are assigned to the same parts or to equivalent parts in eachof the drawings.

First Embodiment

FIG. 1 is a circuit diagram which shows a comparator-system DC-DCconverter according to the first embodiment of the present invention.The comparator-system DC-DC converter 1 shown in FIG. 1 is constitutedby a voltage conversion section 100 and a control unit 200.

The voltage conversion section 100 produces, at an output terminal 3, anoutput voltage Vout obtained by voltage-converting the input voltage Vinwhich is applied to the input terminal 2 in accordance with a switchingcontrol signal Ssw from the control unit 200. That is, the voltageconversion section 100 generates an output voltage Vout across a pair ofoutput terminals which are constituted by an output terminal 3 and anoutput terminal (not shown) which is connected to GND5. The voltageconversion section 100 comprises a switching element 11, a diode 12, adrive circuit 13, an inductor 14, and a capacitor 15.

The switching element 11 is an N-type MOSFET and the two terminalsthereof constitute a current element. The drain of the switching element11 is connected to the input terminal 2 and the source of the switchingelement 11 is connected to the cathode of the diode 12. The anode of thediode 12 is grounded to GND5. The gate of the switching element 11 isconnected to a drive circuit 13.

The drive circuit 13 generates a drive signal in accordance with theswitching control signal Ssw from the control unit 200 and supplies thedrive signal to the gate of the switching element 11.

One end of the inductor 14 is connected to the source of the switchingelement 11 and the cathode of the diode 12. The other end of theinductor 14 is connected to the output terminal 3. A capacitor(smoothing capacitor) 15 for smoothing the output voltage is connectedbetween the other end of the inductor 14 and output terminal 3, andGND5.

The control unit 200 generates a switching control signal Ssw forstabilizing the output voltage Vout of the voltage conversion section100. The control unit 200 comprises a first comparator 20, a timersection 30, a second comparator 40, an SR-FF50, an adjustment section60, an adjustment stoppage section 70, and a reference clock generationsection 80. According to this embodiment, the timer section 30,adjustment section 60, adjustment stoppage section 70, and referenceclock generation section 80 function as frequency control means 25.

The positive input terminal of the first comparator 20 is connected tothe output terminal 3 of the voltage conversion section 100 and areference voltage Vref is input to the negative input terminal. Theoutput terminal of the first comparator 20 is connected to the setterminal of the timer section 30 and SR-FF50.

The timer section 30 comprises a fixed current generation circuit 31, atimer capacitor 32, and a transistor 33. The fixed current generationcircuit 31 is connected between the input terminal 2 and the timercapacitor 32 and supplies a charging current of a constant value to thetimer capacitor 32. The fixed current generation circuit 31 is able tochange the value of the charging current in accordance with a frequencycontrol signal Sf from the adjustment section 60.

The timer capacitor 32 is connected between the fixed current generationcircuit 31 and GND5. The transistor 33 is connected in parallel acrossthe terminals of the timer capacitor 32. That is, the drain of thetransistor 33 is connected to the node between the fixed currentgeneration circuit 31 and one end of the timer capacitor 32 and thesource of the transistor 33 is connected to GND5. An output voltage Vonfrom the first comparator 20 is input to the gate of the transistor 33.

The node between the fixed current generation circuit 31 and one end ofthe timer capacitor 32 is connected to the positive input terminal ofthe second comparator 40. The output voltage Vout is input to thenegative input terminal of the second comparator 40. The output terminalof the second comparator 40 is connected to the reset terminal of theSR-FF50.

The SR-FF50 ends the generation of the OFF pulse and starts thegeneration of the ON pulse of the switching control signal Ssw and endsthe generation of the OFF pulse in accordance with the output voltageVon of the first comparator 20, and ends the generation of the ON pulseof the switching control signal Ssw and starts the generation of the OFFpulse in accordance with the output voltage Voff of the secondcomparator 40. The control signal Ssw is a pulse signal.

Thus, the first comparator 20 detects that the output voltage Vout ofthe voltage conversion section 100 is smaller than the reference voltageVref, sets the SR-FF50 by producing a high-level pulse voltage Von, anddetermines the detection time point as the start time point of the ONpulse of the switching control signal Ssw.

In this embodiment, the fixed current generation circuit 31 receives theinput voltage Vin which is connected to the input terminal 2. However,as long as the output supply source of the fixed current generationcircuit 31 is at predetermined potential difference with respect to GND5and is capable of supplying the output current required for the fixedcurrent generation circuit 31, the fixed current generation circuit 31is not limited to the input voltage Vin of input terminal 2.

Furthermore, the timer section 30 resets the voltage across theterminals of the timer capacitor 32 in accordance with the high-levelpulse voltage Von of the first comparator 20 and subsequently functionsas a timer by charging the timer capacitor 32 by means of a fixedcurrent.

In addition, the second comparator 40 detects that the voltage acrossthe terminals of the timer capacitor 32 of the timer section 30 is equalto or more than the output voltage Vout, that is, detects that apredetermined time has elapsed since the start time point of the ONpulse, and resets the SR-FF50 by producing the high level pulse voltageVoff, and determines the detection time point as the end time point ofthe ON pulse of the switching control signal Ssw.

In other words, the first comparator 20 and second comparator 40function as comparator sections which determine the predetermined ONwidth of the ON pulse of the switching control signal Ssw.

The adjustment section 60 receives the switching control signal Ssw anda reference clock Cref which is generated by the reference clockgeneration section 80. The adjustment section 60 compares the switchingcontrol signal Ssw with the reference clock Cref and adjusts thepredetermined ON width of the ON pulse so that the frequency of theswitching control signal Ssw is constant in accordance with thecomparison result. More specifically, the adjustment section 60 countsthe ON pulses of the switching control signal Ssw, counts the referenceclocks, and generates the frequency control signal Sf for adjusting thepredetermined ON width of the ON pulse so that the count value of theswitching control signal Ssw and the count value of the reference clockare equal. In the comparator-system DC-DC converter according to thisembodiment, a frequency control signal Sf is a 4-bit digital signal.

The input terminal of the adjustment stoppage section 70 is connected toone end of the inductor 14 and the output terminal is connected to thereference clock generation section 80. The switching control signal Sswis input to the reset terminal of the adjustment stoppage section 70.The adjustment stoppage section 70 detects the output current IL thatflows in a direction toward the inductor 14 from the switching element11 or the diode 12 and, in cases where the value of the output currentIL is 0 A, stops the processing to adjust the predetermined ON width ofthe ON pulse. More specifically, the adjustment stoppage section 70generates an adjustment stoppage signal Sstop for stopping the referenceclock generation section 80 from the point where the resonance voltageV11 produced at one end of the inductor 14 is detected when the value ofthe output current IL is 0 A until the time point where the ON pulse ofthe switching control signal Ssw is produced.

The reference clock generation section 80 generates the reference clockCref and stops the generation of the reference clock Cref in accordancewith the adjustment stoppage signal Sstop from the adjustment stoppagesection 70. More specifically, the reference clock generation section 80latches the voltage level of the reference clock Cref in accordance withthe adjustment stoppage signal Sstop and stops the generation of thereference clock Cref.

The timer section 30, adjustment section 60, adjustment stoppage section70, and reference clock generation section 80 will be described next indetail. FIG. 2 is a circuit which shows the timer section 30 of FIG. 1and FIG. 3 is a circuit diagram which shows the adjustment section 60 ofFIG. 1. Furthermore, FIG. 4 is a circuit diagram which shows theadjustment stoppage section 70 of FIG. 1 and FIG. 5 is a circuit diagramwhich shows the reference clock generation section 80 of FIG. 1.

First, the timer section 30 will be described. FIG. 2 shows the fixedcurrent generation circuit 31 of the timer section 30 in detail. Thefixed current generation circuit 31 comprises an input voltage divisioncircuit 34, a voltage follower 35, a resistance element 36, a currentmirror circuit 37, a gm amplifier 38, and a digital/analog conversionsection (known as a ‘DAC’ hereinbelow) 39.

The input voltage division circuit 34 divides the input voltage Vinwhich is input from the input terminal 2. In this embodiment, the inputvoltage division circuit 34 is constituted by resistance elements 34 aand 34 b which are connected in series between the input terminal 2 andGND5. The divided voltage between the resistance elements 34 a and 34 bis input to the voltage follower 35.

The voltage follower 35 is constituted by an error difference amplifier35 a and a transistor 35 b. In this embodiment, the transistor 35 b isan n-type MOSFET. The resistance element 36 is connected between thesource of the transistor 35 b and GND5. Furthermore, the current mirrorcircuit 37 is connected between the drain of the transistor 35 b and theinput terminal 2.

The current mirror circuit 37 is constituted by a transistor 37 athrough which a reference current determined by the voltage follower 35flows and a transistor 37 b which generates a mirror current of thereference current which flows to the transistor 37 a. In thisembodiment, the transistors 37 a and 37 b are p-type MOSFETs. Thetransistor 37 b supplies this mirror current to the timer capacitor 32.

The DAC 39 converts the 4-bit digital frequency control signal Sf fromthe adjustment section 60 into an analog signal. The output terminal ofthe DAC 39 is connected to one input terminal of the gm amplifier 38.

The reference voltage Vref2 is input to the other input terminal of thegm amplifier 38. The output terminal of the gm amplifier 38 is connectedto a node between the transistor 37 a of the current mirror circuit 37and the voltage follower 35.

The gm amplifier 38 functions as a push/pull-type current source,drawing a current from the transistor 37 a of the current mirror circuit37 when the output signal of the DAC 39 is equal to or more than thereference voltage Vref2, for example, and supplying a current to thevoltage follower 35 when the output signal of the DAC 39 is smaller thanthe reference voltage Vref2. In other words, the gm amplifier 38increases the charging current of the timer capacitor 32 when Sf isequal to or more than Vref2 and reduces the charging current of thetimer capacitor 32 when Sf is smaller than Vref2.

The adjustment section 60 will be described next. As shown in FIG. 3,the adjustment section 60 comprises two counters 61 and 62 and anup/down counter 68.

A switching control signal Ssw is input to the input terminal of thefirst counter 61 and the output voltage of the second counter 62 isinput to the reset terminal of the first counter 61. For example, thefirst counter 61 is a 4-bit counter. The first counter 61 counts the ONpulse of the switching control signal Ssw and, in cases where the countvalue reaches the maximum value ‘1111’, outputs the high-level pulsevoltage Vdown and resets the output voltage at the next count of ‘1111’.In addition, the first counter 61 also resets the output voltage whenthe output voltage of the second counter 62 has reached a high level.The output terminal of the first counter 61 is connected to one inputterminal of the up/down counter 68.

The reference clock Cref is input to the input terminal of the secondcounter 62 and the output voltage of the first counter 61 is input tothe reset terminal of the second counter 62. The second counter 62 is a4-bit counter, for example. The second counter 62 counts the referenceclock cycles and, in cases where the count value has reached a maximumvalue ‘1111’, outputs a high-level pulse voltage Vup and resets theoutput voltage at the next count of ‘1111’. In addition, the secondcounter 62 also resets the output voltage when the output voltage of thefirst counter 61 has reached a high level. The output terminal of thesecond counter 62 is connected to the other input terminal of theup/down counter 68.

The up/down counter 68 receives the pulse voltage from the first counter61 and the pulse voltages Vdown and Vup from the second counter 62 andincreases or reduces the count value. In this embodiment, the up/downcounter 68 reduces the count value when a high-level pulse voltage Vdownis input by the first counter 61 and increases the count value when ahigh-level pulse voltage Vup is input by the second counter 62. Theup/down counter 68 outputs the 4-bit digital frequency control signal Sfto the timer section 30.

The adjustment stoppage section 70 will be described next. As shown inFIG. 4, the adjustment stoppage section 70 comprises a detected voltagedivision circuit 71, a comparator 72, a Zener diode 73, and a D-FF74.

The detected voltage division circuit 71 divides the voltage V11 of oneend of the inductor 14. In this embodiment, the detected voltagedivision circuit 71 is constituted by resistance elements 71 a and 71 bwhich are connected in series between one end of the inductor 14 andGND5. The divided voltage between the resistance elements 71 a and 71 bis input to the positive input terminal of the comparator 72.

The Zener diode 73 is connected between the positive input terminal ofthe comparator 72 and GND5. Here, the voltage V11 at one end of theinductor 14 rises to the input voltage Vin when the switching element 11enters an ON state. The Zener diode 73 is provided in order to provideovervoltage protection for the input terminal of the comparator 72.

A reference voltage Vref3 is input to the negative input terminal of thecomparator 72. The comparator 72 outputs a high-level pulse voltage whenthe resonance voltage V11 is produced at one end of the inductor 14 andthe divided voltage between the resistance elements 71 a and 71 b isgreater than the reference voltage Vref3. Thus, the comparator 72functions as a current detection section which detects the time point atwhich the output current IL reaches 0 A by detecting the occurrence ofthe resonance voltage V11 at one end of the inductor 14. The outputterminal of the comparator 72 is connected to the clock terminal of theD-FF74.

The input voltage Vin is input to the input terminal of the D-FF74 andthe switching control signal Ssw is input to the reset terminal. TheD-FF74 generates a high-level adjustment stoppage signal Sstop in theperiod from the time point at which a high-level pulse voltage isreceived from the comparator 72 until the time point at which ahigh-level switching control signal Ssw is received, that is, the periodin which the output current IL is 0 A.

The reference clock generation section 80 will be described next. Asshown in FIG. 5, the reference clock generation section 80 comprises anoscillator 81, an EXOR circuit 82, three D-FF83, 84, and 85.

The adjustment stoppage signal Sstop is input to one input terminal ofthe EXOR circuit 82 while the other input terminal is connected to theinverting output terminal of the D-FF83. The output terminal of the EXORcircuit 82 is connected to the input terminal of the D-FF83.

Clocks from the oscillator 81 are input to the clock terminal of theD-FF83 and the non-inverting output terminal is connected to the clockterminal of the D-FF84.

The input terminal of the D-FF84 is connected to the inverting outputterminal and the output terminal of the D-FF84 is connected to the clockterminal of the D-FF85. Likewise, the input terminal of the D-FF85 isconnected to the inverting output terminal and the D-FF85 outputs thereference clock Cref from the non-inverting output terminal.

Thus, the EXOR 82 and the D-FF 83, 84, and 85 constitute a clockdivision circuit and generate the reference clock Cref, which isobtained by dividing the clock from the oscillator into eight, when theadjustment stoppage signal Sstop is at a low level. In addition, theclock division circuit latches the voltage level of the reference clockCref and stops the reference clock Cref when the adjustment stoppagesignal Sstop is at a high level signal. In other words, the clockdivision circuit lowers the frequency of the reference clock Cref whenthe adjustment stoppage signal Sstop is a high level signal.

The operation of the comparator-system DC-DC converter 1 will bedescribed next. FIG. 6 is a timing chart which shows the respectivesignal waveforms of the continuous current mode of the comparator-systemDC-DC converter 1 shown in FIG. 1 and FIG. 7 is a timing chart whichshows the respective signal waveforms of the continuous current mode ofthe adjustment section 60 shown in FIG. 3.

First, when the input voltage Vin is input to the input terminal 2, theswitching control signal Ssw is generated by the control unit 200. Thevoltage conversion section 100 produces a stabilized output voltage Voutat the output terminal 3 in accordance with the switching control signalSsw.

Here, in cases where the load current is relatively large, thecomparator-system DC-DC converter 1 operates in continuous current modein which the output current is always greater than 0 A. Here, the ONpulse width Pon is set so that the switching frequency matches thefrequency of the reference clock Cref.

When the output voltage Vout drops and reaches the reference voltageVref ((a) of FIG. 6), a high-level pulse voltage Von is generated by thefirst comparator 20 ((c) of FIG. 6) and ON pulse Pon is produced fromstart time point Ta in the switching control signal Ssw by the SR-FF50and the production of the OFF pulse Poff ends at time point Ta ((e) ofFIG. 6). Thereupon, a high level drive signal is generated by the drivecircuit 13 and the switching element 11 enters an ON state. As a result,the output current IL which flows to the inductor 14 increases and theoutput voltage Vout rises ((a) and (b) of FIG. 6).

When a high-level pulse voltage Von is generated by the first converter20, the transistor 33 temporarily enters an ON state and the voltageacross the terminals of the timer capacitor 32 is reset, whereupon thetimer capacitor 32 is gradually charged by the fixed current from thefixed current generation circuit 31. When the voltage across theterminals of the timer capacitor 32 reaches the output voltage Vout, ahigh level pulse voltage Voff is generated by the second comparator 40((d) of FIG. 6), the OFF pulse Poff is produced from time point Tb inthe switching control signal Ssw by the SR-FF50, and the production ofthe ON pulse Pon ends at end time point Tb ((e) of FIG. 6). Thereupon,the drive signal is changed from a high level to a low level by thedrive circuit 13 and the switching element 11 enters an OFF state. As aresult, the output voltage Vout drops due to the power consumption ofthe connected load, and the output current IL decreases. The outputvoltage Vout is stabilized due to the repetition of the above operation.

Further, when the ambient temperature drops, for example, the internalresistance values of the switching element 11, diode 12, and inductor 14or the like, for example, drop and the internal loss is reduced.Thereupon, in order to compensate for a rise in the output voltage Vout,the OFF width of the OFF pulse Poff increases and the ON duty isreduced. Meanwhile, the predetermined ON width of the ON pulse Pon isadjusted by the adjustment section 60.

More specifically, because the switching frequency of the switchingcontrol signal Ssw is lower than the frequency of the reference clockCref ((a) and (c) of FIG. 7), the second counter 62 ends the countbefore the first counter 61 and outputs a high level pulse voltage Vup((b) of FIG. 7). However, the output voltage Vdown of the first counter61 remains at a low level ((d) of FIG. 7). As a result, the up/downcounter 68 raises the value of the frequency control signal Sf ((e) ofFIG. 7).

Thereupon, the gm amplifier 38 draws a current which is proportional tothe differential voltage between the frequency control signal Sf and thereference voltage Vref2 and increases the charging current of the timercapacitor 32. As a result, the time taken for the voltage Vt across theterminals of the timer capacitor 32 to reach the output voltage Voutgrows short and the end time point Tb of the ON pulse Pon is earlier. Asa result, the ON width of the ON pulse Pon grows narrow and, because theON duty is fixed by Vin and Vout, the OFF width of the OFF pulse Poffalso narrows and the switching frequency rises. Thus, the adjustmentsection 60 controls the switching frequency so that same approaches thefrequency of the reference clock Cref and the fluctuations in theswitching frequency are therefore reduced.

However, when the ambient temperature rises, for example, the internalresistance values of the switching element 11, diode 12, and inductor14, and so forth, for example, increase and the internal loss increases.Thereupon, in order to compensate for a drop in the output voltage Vout,the OFF width of the OFF pulse Poff narrows and the ON duty isincreased. Meanwhile, the predetermined ON width of the ON pulse Pon isadjusted by the adjustment section 60.

More specifically, because the switching frequency of the switchingcontrol signal Ssw is higher than the frequency of the reference clockCref, the first counter 61 ends the count before the second counter 62and outputs a high-level pulse voltage Vdown. However, the outputvoltage Vup of the second counter 62 remains at a low level. As aresult, the up/down counter 68 reduces the value of the frequencycontrol signal Sf.

Thereupon, the gm amplifier 38 outputs a current which is proportionalto the differential voltage between the frequency control signal Sf andthe reference voltage Vref2 and reduces the charging current of thetimer capacitor 32. As a result, the time taken for the voltage Vtacross the terminals of the timer capacitor 32 to reach the outputvoltage Vout grows long and the end time point Tb of the ON pulse Pon isdelayed. As a result, the ON width of the ON pulse Pon grows increasesand, because the ON duty is fixed by Vm and Vout, the OFF width of theOFF pulse Poff also narrows and the switching frequency decreases. Thus,the adjustment section 60 controls the switching frequency so that sameapproaches the frequency of the reference clock Cref and thefluctuations in the switching frequency are therefore reduced.

The operation in the discontinuous current mode of the comparator-systemDC-DC converter 1 will be described next. In cases where the loadcurrent is relatively small, the comparator-system DC-DC converter 1operates in the discontinuous current mode in the period during whichthe output current is 0 A arises. Here, the adjustment processing tomatch the switching frequency with the frequency of the reference clockCref is temporarily stopped and a narrowing of the ON width of the ONpulse is suppressed.

FIG. 8 is a timing chart which shows the respective signal waveforms inthe discontinuous current mode of the comparator-system DC-DC converter1 shown in FIG. 1 and FIG. 9 is a timing chart which shows therespective signal waveforms of the discontinuous current mode of thereference clock generation section 80 shown in FIG. 5. Furthermore, FIG.10 is a timing chart which shows the respective signal waveforms of thediscontinuous current mode of the adjustment section 60 shown in FIG. 3.

In the event of a light load with a small load current, the timerequired to discharge the capacitor 15 is long and the drop time of theoutput voltage Vout increases ((a) of FIG. 8). Hence, the width of theOFF pulse Poff of the switching control signal Ssw increases and thefrequency of the switching control signal Ssw drops ((e) of FIG. 8).Thereupon, in the period of the generation of the OFF pulse Poff, aperiod P0 in which the output current IL is 0 A occurs ((b) of FIG. 8)and the resonance voltage V11 is produced at one end of the inductor 14from the time point at which the output current IL is 0 A ((f) of FIG.8). The comparator 72 of the adjustment stoppage section 70 detects thatthe resonance voltage V11 is greater than the reference voltage Vref3and outputs a high-level pulse voltage. Thereupon, a high-leveladjustment stoppage signal Sstop is output by the D-FF74 ((g) of FIG.8). The generation of a high-level adjustment stoppage signal Sstop bythe D-FF74 continues until the start time point Ta of the generation ofthe ON pulse Pon in the switching control signal Ssw which is input tothe reset terminal ((e) of FIG. 8). Thus, a high-level adjustmentstoppage signal Sstop is generated by the adjustment stoppage section 70in the period P0 in which the output current IL is 0 A.

When a high-level adjustment stoppage signal Sstop is generated ((a) ofFIG. 9), the output voltage of the EXOR 82 of the reference clockgeneration section 80 is inverted and the level of a non-invertingoutput voltage Q of the D-FF83 is latched and the level of thenon-inverting output voltage Q of the D-FF84 is latched ((d) of FIG. 9)in the period P0 in which the output current IL is 0 A ((c) of FIG. 9).As a result, the level of the reference clock Cref output by the D-FF85is latched in the period P0 in which the output current IL is 0 A.

Thus, when the adjustment stoppage signal Sstop is generated ((b) ofFIG. 10) by the adjustment stoppage section 70 in accordance with theresonance voltage V11 at one end of the inductor 14 ((a) of FIG. 10),the voltage level of the reference clock Cref is latched ((c) of FIG.10). As a result, the frequency of the reference clock Cref drops so asto approach the frequency of the switching control signal Ssw ((c) and(e) of FIG. 10), the count of the second counter 62 is delayed.Thereupon, the generation of the high-level pulse voltage Vup issuppressed ((d) of FIG. 10), and an increase in the frequency controlsignal Sf is suppressed ((g) of FIG. 10). As a result, even when thefrequency of the switching control signal Ssw drops in the discontinuouscurrent mode, the adjustment of the ON width of the ON pulse Pon issuppressed and a narrowing of the ON width of the ON pulse Pon issuppressed.

FIG. 11 shows the switching frequency characteristic with respect to theload current of the comparator-system DC-DC converter 1 shown in FIG. 1.FIG. 11 shows the simulation effect of a comparator-system DC-DCconverter of a comparative example in addition to the simulation effectof the comparator-system DC-DC converter 1 of this embodiment.

Curve A shows the simulation effect of the comparator-system DC-DCconverter 1 of this embodiment. Curve B shows the simulation effect of acomparator-system asynchronous rectification DC-DC converter of aComparative Example 1 which is a constitution not comprising theadjustment section 60 and adjustment stoppage section 70 of thecomparator-system DC-DC converter 1 of this embodiment. Curve C showsthe simulation effect of a comparator-system synchronous rectificationDC-DC converter of a Comparative Example 2 which is a constitution notcomprising the adjustment stoppage section 70 of the comparator-systemDC-DC converter 1 of this embodiment.

As indicated by curve C, the comparator-system asynchronousrectification DC-DC converter of Comparative Example 1 produces anincrease in the switching frequency as the load current increases in thecontinuous current mode. Hence, due to fluctuations in the switchingfrequency in the continuous current mode which is the actual usagestate, the ripple of the output voltage fluctuates and there is thepossibility of a downstream circuit such as the PU operatingerroneously. There is also the possibility of ENI countermeasuresextending over a wide bandwidth being required.

Furthermore, as indicated by curve C, the comparator-system synchronousrectification DC-DC converter of Comparative Example 2 sometimesover-reduces the ON width of the switching waveform in an attempt tokeep the switching frequency constant when the load current decreases inthe discontinuous current mode. Irrespective of whether the load currentis small, the loss increases as a result of switching with a narrow ONwidth being performed at a high frequency. Hence, the power consumedcannot be adequately reduced.

In contrast, as indicated by curve A, the switching frequency can bekept constant in the continuous current mode as a result of providingthe adjustment section 60 and adjustment stoppage section 70 as per thecomparator-system DC-DC converter 1 of this embodiment, and an excessivenarrowing of the ON width can be suppressed by stopping the processingto adjust the switching frequency in the discontinuous current mode.

Thus, according to the comparator-system DC-DC converter 1 of the firstembodiment, in the continuous current mode, the fluctuations in theswitching frequency which arise due to fluctuations in the conversionloss due to fluctuations in the ambient temperature, fluctuations in theI/O voltages, and fluctuations in the output current can be reducedwithout impairing the response characteristic with respect to a suddenincrease in the load current. As a result, in the continuous currentmode, fluctuations in the output voltage ripple can be reduced anderroneous operation of a downstream circuit such as the PU can beprevented. Furthermore, EMI countermeasures extending over a widebandwidth are not required, and EMI countermeasures can be carried outinexpensively and in a straightforward manner.

However, in discontinuous current mode, processing to adjust the ONwidth of the ON pulse can be stopped in the period in which the outputcurrent is 0 A. Accordingly, the fact that the ON width of the ON pulsenarrows greatly can be suppressed in discontinuous current mode anddisturbance of the switching waveform can be reduced. In addition, thereis no need to employ costly circuit elements with a high-speedcharacteristic. In addition, the loss caused by performing switchingwith a narrow ON width at a high frequency can be suppressedirrespective of whether the load current is small. Hence, the powerconsumption can be reduced.

Second Embodiment

FIG. 12 is a circuit diagram which shows a comparator-system DC-DCconverter according to the second embodiment of the present invention.The comparator-system DC-DC converter 1A shown in FIG. 12 differs fromthe comparator-system DC-DC converter 1 in the first embodiment in thatthe comparator-system DC-DC converter 1A comprises a voltage conversionsection 100A and a control unit 200A in place of the voltage conversionsection 100 and control unit 200 of the comparator-system DC-DCconverter 1.

The voltage conversion section 100A further comprises a resistanceelement (current detection resistance element) 16 which is seriallyconnected to the inductor 14 in the voltage conversion section 100. Theremaining constitution of the voltage conversion section 100A is thesame as that of the voltage conversion section 100.

The control unit 200A differs from the control unit 200 in that thecontrol unit 200A comprises an adjustment stoppage section 70A insteadof the adjustment stoppage section 70 of the control unit 200. Theremaining constitution of the control unit 200A is the same as that ofthe control unit 200. In this embodiment, the timer section 30,adjustment section 60, adjustment stoppage section 70A, and referenceclock generation section 80 function as frequency control means 25A.

FIG. 13 is a circuit diagram which shows an adjustment stoppage section70A shown in FIG. 12. The adjustment stoppage section 70A shown in FIG.13 differs from the adjustment stoppage section 70 in that theadjustment stoppage section 70A does not comprise the detected voltagedivision circuit 71 and Zener diode 73 of the adjustment stoppagesection 70.

The comparator 72 detects the voltage across the terminals of theresistance element 16 in order to detect the output current IL. Morespecifically, the positive input terminal of the comparator 72 isconnected to a node between the inductor 14 and resistance element 16and the negative input terminal is connected to a node between theresistance element 16 and output terminal Vout. In other words, avoltage V111 which is a high voltage is input in continuous current modeto the negative input terminal of the comparator 72 and a voltage V112which is a low voltage is input to the positive input terminal. Thecomparator 72 detects that the voltage V111 and voltage V112 are to beequal or mutually inverted and outputs a high-level pulse voltage. Thus,the comparator 72 functions as a current detection section which detectsa state where the output current IL is 0 A or a state where the outputcurrent is going to be 0 A by detecting the voltage difference betweenvoltage V111 and voltage V112. The detection of the state where theoutput current IL is going to be 0 A can be implemented by applying apredetermined forward-bias voltage to the positive input terminal of thecomparator 72, for example.

The same benefits as those of the first embodiment can also be obtainedby the comparator-system DC-DC converter 1A of the second embodiment.

Third Embodiment

FIG. 14 is a circuit diagram which shows a comparator-system DC-DCconverter according to the third embodiment of the present invention.The comparator-system DC-DC converter 1B shown in FIG. 14 differs fromthe comparator-system DC-DC converter 1 in the first embodiment in thatthe comparator-system DC-DC converter 1B comprises a control unit 200Bin place of the control unit 200 of the comparator-system DC-DCconverter 1. The remaining constitution of the comparator-system DC-DCconverter 1B is the same as that of the comparator-system DC-DCconverter 1.

The control unit 200B comprises an adjustment section 60B in place ofthe adjustment section 60 in the control unit 200. Furthermore, thecontrol unit 200B differs from the control unit 200 in that the controlunit 200B uses an externally generated reference clock Cref and does notcomprise the reference clock generation section 80 of the control unit200. The remaining constitution of the control unit 200B is the same asthat of the control unit 200. In this embodiment, the timer section 30,adjustment section 60B, and adjustment stoppage section 70B function asfrequency control means 25B.

FIG. 15 is a circuit diagram which shows the adjustment section 60Bwhich is shown in FIG. 14. The adjustment section 60B which is shown inFIG. 15 differs from the adjustment section 60 in that the adjustmentstoppage signal Sstop which is output by the adjustment stoppage section70 is input to each of the control terminals of the first counter 61 andsecond counter 62. The remaining constitution of the adjustment section60B is the same as that of the adjustment section 60.

FIG. 16 is a timing chart which shows the respective signal waveforms inthe discontinuous current mode of the adjustment section 60B which isshown in FIG. 15.

When a high-level adjustment stoppage signal Sstop is input to the firstcounter 61 and second counter 62 ((b) of FIG. 16), the first counter 61and second counter 62 stop counting (time point Ts of (c) of FIG. 16).In other words, the first counter 61 and second counter 62 reset thecount values, that is, the output voltages.

As a result, when the output current reaches 0 A in the discontinuouscurrent mode, because the count values are reset prior to the firstcounter 61 and second counter 62 ending the count up to a predeterminedvalue, a high-level pulse voltage Vup is not produced ((d) of FIG. 16)and the frequency control signal Sf does not rise ((g) of FIG. 16). As aresult, even when the frequency of the switching control signal Sswdrops in the discontinuous current mode, the adjustment of the ON widthof the ON pulse Pon is stopped.

Thus, the comparator-system DC-DC converter 1B of the third embodimentalso allows the same benefits as those of the first embodiment to beobtained.

Fourth Embodiment

FIG. 17 is a circuit diagram which shows a comparator-system DC-DCconverter according to the fourth embodiment of the present invention.The comparator-system DC-DC converter 1C which is shown in FIG. 17differs from the comparator-system DC-DC converter 1B in the thirdembodiment in that the comparator-system DC-DC converter 1C comprises acontrol unit 200C in place of the control unit 200B of thecomparator-system DC-DC converter 1B. The remaining constitution of thecomparator-system DC-DC converter 1C is the same as that of thecomparator-system DC-DC converter 1B.

The control unit 200C differs from the control unit 200B in that thecontrol unit 200C comprises an adjustment section 60C and an adjustmentstoppage section 70C in place of the adjustment section 60B andadjustment stoppage section 70 of the control unit 200B. The remainingconstitution of the control unit 200C is the same as that of the controlunit 200B. In this embodiment, the timer section 30, adjustment section60C, and adjustment stoppage section 70C function as frequency controlmeans 25C.

FIG. 18 is a circuit diagram which shows the adjustment stoppage section70C which is shown in FIG. 17. The adjustment stoppage section 70C whichis shown in FIG. 18 differs from the adjustment stoppage section 70 inthe third embodiment in that the stoppage section 70C further comprisesa delay reset signal generation section 75. The remaining constitutionof the adjustment stoppage section 70C is the same as that of theadjustment stoppage section 70.

The adjustment stoppage section 70C comprises a delay circuit 75 a whichdelays the phase of the switching control signal Ssw, a NOT circuit 75 bwhich inverts the switching control signal Ssw, and an AND circuit 75 cthe two input terminals of which are connected to a delay circuit 75 aand a NOT circuit 75 b. The adjustment stoppage section 70C generates ahigh-level pulse voltage at the end time point of the ON pulse of theswitching control signal Ssw and supplies same to the reset terminal ofthe D-FF74.

FIG. 19 is a circuit diagram which shows an adjustment section 60C whichis shown in FIG. 17. The adjustment section 60C which is shown in FIG.19 differs from the adjustment section 60 in that the adjustment section60C further comprises a multiplexer 69. The remaining constitution ofthe adjustment section 60C is the same as that of the adjustment section60.

One input terminal of the multiplexer 69 is connected to the outputterminal of the up/down counter 68 and a fixed value is input to theother input terminal. The adjustment stoppage signal Sstop is input tothe control terminal of the multiplexer 69. The multiplexer 69 selectsthe output signal of the up/down counter 68 when the adjustment stoppagesignal. Sstop is a low-level signal and outputs the output signal as thefrequency control signal Sf. The multiplexer 69 selects a fixed valuewhen the adjustment stoppage signal Sstop is a high-level signal andoutputs the fixed value as the frequency control signal Sf.

The adjustment stoppage signal Sstop is also input to the controlterminal of the up/down counter 68.

FIG. 20 is a timing chart which shows the respective signal waveforms ofthe discontinuous current mode of the adjustment stoppage section 70Cwhich is shown in FIG. 18. As shown in FIG. 20, when the resonancevoltage V11 at one end of the inductor 14 is detected by the comparator72 ((a) of FIG. 20), the generation of a high-level adjustment stoppagesignal Sstop is started by the D-FF74. Thereafter, a high-level pulsevoltage Sr is generated by a delay reset circuit at the end time pointTb of the ON pulse Pon of the switching control signal Ssw ((b) of FIG.20) and the generation of the high-level adjustment stoppage signalSstop is terminated by the D-FF74 ((c) of FIG. 20).

When a high-level adjustment stoppage signal Sstop is generated, theup/down counter 68 stops counting and the multiplexer 69 changes fromthe output signal of the up/down counter 68 to a fixed value and outputssame as the frequency control signal Sf.

Thus, the comparator-system DC-DC converter 1C of the fourth embodimentmakes it possible to stop the adjustment processing of the ON width ofthe ON pulse until the ON pulse production period in addition to periodsin which the output current is equal to or less than 0 A. As a result,the count of the up/down counter 68 can be delayed and the adjustment ofthe ON width of the ON pulse can be suppressed. Therefore, thecomparator-system DC-DC converter 1C of the fourth embodiment also makesit possible to obtain the same benefits as the third embodiment.

The present invention is not limited to the above embodiments and can bemodified in a variety of ways.

Although this embodiment takes the example of a digital circuit whichgenerates a digital frequency control signal Sf as the adjustmentsection 60, an analog circuit which generates an analog frequencycontrol signal Sf is also applicable. FIG. 21 is a circuit diagram whichshows the adjustment section according to a modified example 1. Theadjustment section 60X of the modified example 1 shown in FIG. 21comprises a NOR circuit 63 in place of the up/down counter 68 in theadjustment section 60, a NAND circuit 64, two inverters 65 and 66, acharge pump circuit 67, and an adjustment capacitor 68X. The remainingconstitution of the adjustment section 60X is the same as that of theadjustment section 60.

One input terminal of the NOR circuit 63 is connected to the outputterminal of the first counter 61 via the inverter 65 and the other inputterminal is connected to the output terminal of the second counter 62.The output terminal of the NOR circuit 63 is connected to the chargepump circuit 67.

One input terminal of the NAND circuit 64 is connected to the outputterminal of the second counter 62 and the other input terminal isconnected to the output terminal of the first counter 61 via theinverter 66. The output terminal of the NAND circuit 64 is connected tothe charge pump circuit 67.

The charge pump circuit 67 is constituted by a transistor 67 aconsisting of an n-type MOSFET, a transistor 67 b consisting of a p-typeMOSFET, and two fixed current sources 67 c and 67 d. The source of thetransistor 67 a is connected to the GND5 via the fixed current source 67c and the drain of the transistor 67 a is connected to the drain of thetransistor 67 b. The source of the transistor 67 b has an input voltageVin input thereto via the fixed current source 67 d. A pulse voltageVdown which is output by the NOR circuit 63 and the pulse voltage Vupwhich is output by the NAND circuit 64 are input to the respective gatesof the transistors 67 a and 67 b. The adjustment capacitor 68X isconnected between the drain of the transistors 67 a and 67 b and GND5.

In the adjustment section 60X, in cases where the frequency of theswitching control signal Ssw is lower than the frequency of thereference clock Cref, the first counter 61 ends the count before thesecond counter 62 and generates an output voltage at a high level, andthe NAND circuit 64 outputs a low level pulse voltage Vup. Hence, thecapacitor 68X is charged by the charge pump circuit 67 and the level ofthe frequency control signal Sf rises. However, in cases where thefrequency of the switching control signal Ssw is higher than thefrequency of the reference clock Cref, the second counter 62 ends thecount before the first counter 61 and generates an output voltage at ahigh level, and the NOR circuit 63 outputs a high-level pulse voltageVdown. Hence, the capacitor 68X is discharged by the charge pump circuit67 and the level of the frequency control signal Sf drops.

According to Modified example 1, input voltage Vin is input to thesource of the transistor 67 b via the fixed current source 67 d.However, in the case of a power source which comprises a predeterminedpotential difference from the GND5 and which is capable of supplying theoutput current which is required for the fixed current sources 67 c and67 d, there are no restrictions on the input voltage Vin of the inputterminal 2.

In addition, a circuit which employs a phase comparator is alsoapplicable to the adjustment section 60. FIG. 22 is a circuit diagramwhich shows the adjustment section according to Modified example 2. Theadjustment section 60Y of Modified example 2 shown in FIG. 22 comprisesa phase comparator 61Y in place of the first and second counters 61 and62 respectively, the NOR circuit 63, the NAND circuit 64, and the twoinverters 65 and 66 in the adjustment section 60X. The remainingconstitution of the adjustment section 60Y is the same as that of theadjustment section 60X.

The switching control signal Ssw is input to one input terminal of thephase comparator 61Y while the reference clock Cref is input to theother input terminal. The phase comparator 61Y compares the phase of theswitching control signal Ssw with the phase of the reference clock Crefand generates the output voltages Vdown and Vup which have values whichcorrespond with the phase difference between the Ssw and Cref indicatedby the comparison result. The phase comparator 61Y supplies the outputvoltage Vdown to the gate of the transistor 67 a of the charge pumpcircuit 67 and supplies the output voltage Vup to the gate of thetransistor 67 b of the charge pump circuit 67.

In the adjustment section 60Y, in cases where the frequency of theswitching control signal Ssw is lower than the frequency of thereference clock Cref, the phase comparator 61Y outputs a low-level pulsevoltage Vup and the capacitor 68X is charged by the charge pump circuit67 and the level of the frequency control signal Sf rises. However, incases where the frequency of the switching control signal Ssw is higherthan the frequency of the reference clock Cref, the phase comparator 61Youtputs the high-level pulse voltage Vdown and, therefore, the capacitor68X is discharged by the charge pump circuit 67 and the level of thefrequency control signal Sf drops.

Furthermore, this embodiment illustrates an output current detectionmethod which detects the period in which the output current is equal toor less than 0 A by means of a resonance voltage at one end of theinductor 14 and an output current detection method which detects a statewhere the output current is equal to or less than 0 A or going to be 0 Aby means of the voltage across the two terminals of the resistanceelement 16 which is serially connected to the inductor 14. However, theoutput current detection method is not limited to this embodiment. Theoutput current detection method shown in FIG. 23 is also applicable, forexample. FIG. 23 shows the current detection method according to amodified example. As shown in FIG. 23, the serial circuit between theresistance element (current detection resistance element) 17 and thecapacitor (current detection capacitor) 18 is connected in parallel tothe inductor 14 and the time point at which the output current IL isgoing to become 0 A or OV may be detected by detecting the time point atwhich the voltage across the terminals of the capacitor 18 is 0V orgoing to be 0V.

In addition, although this embodiment illustrates a method which stopsthe clock division circuits 82, 83, 84, and 85 of the reference clockgeneration section 80 as the method for stopping the adjustment of thepredetermined ON width, the reference clock generation circuit itselfmay also be stopped. FIG. 24 is a circuit diagram which shows thereference clock generation section according to a modified example. Thereference clock generation section 80X of the modified example shown inFIG. 24 is a ring oscillator which comprises a triangular wavegeneration circuit 86, a comparator 87, a D-FF circuit 88, and aone-shot pulse signal generation circuit 89. FIG. 25 is a respectivepart signal waveform for the reference clock generation sectionaccording to the modified example.

The triangular wave generation circuit 86 comprises a fixed currentsource 86 a which is serially connected in order between the terminal towhich the input voltage Vin is input and the terminal connected to theGND5, a switch element 86 b, and a capacitor 86 c. The triangular wavegeneration circuit 86 further comprises a switch element 86 d which isconnected in parallel to the capacitor 86 c. The switch element 86 benters an ON state when the adjustment stoppage signal Sstop is a lowlevel signal. However, the switch element 86 d enters an ON state when ahigh-level pulse voltage is output by the one-shot pulse signalgeneration circuit 89. Thus, the triangular wave generation circuit 86generates a saw-wave-shaped triangular wave voltage when the adjustmentstoppage signal Sstop is a low level signal ((a), (b), and (d) of FIG.25). The comparator 87 compares the triangular wave voltage withreference voltage Vref4 from the triangular wave generation circuit 86and generates a low-level output voltage when the triangular wavevoltage is smaller than the reference voltage Vref4 and generates ahigh-level pulse voltage when the triangular wave voltage is equal to ormore than the reference voltage Vref4 ((b) and (c) of FIG. 25). Theinput terminal of the D-FF circuit 88 is connected to the invertingoutput terminal and the output voltage from the comparator 87 is inputto the clock terminal. The D-FF circuit 88 inverts the level of thereference clock Cref in accordance with the pulse voltage from thecomparator 87. The one-shot pulse signal generation circuit 89 outputs apulse voltage when the level of the reference clock Cref is inverted.

Here, when the adjustment stoppage signal Sstop is a high level signal,the switch element 86 b enters an OFF state, the charging of thecapacitor is stopped, and the level of the triangular wave voltage fromthe triangular wave generation circuit 86 is latched. As a result, thelevel of the reference clock Cref is latched. Thus, the reference clockgeneration section 80X of the modified example is able to stop thegeneration of the reference clock Cref by stopping the reference clockgeneration circuit itself in accordance with the adjustment stoppagesignal Sstop.

In addition, in this embodiment, the timer section 30 controls the ONtime width Pon but may also control the OFF time width Poff. In thiscase, the drive circuit 13 generates a drive signal such that theswitching element 11 enters an OFF state when the switching controlsignal Ssw is at a high level. In addition, in this case, the adjustmentsection 60 adjusts the OFF time width Poff instead of the ON time widthPon.

Furthermore, the method for changing the ON width of the ON pulse Pon ofthe switching control signal Sw is not limited to that of thisembodiment. Rather, a variety of method forms may be considered. Forexample, the charging current of the timer capacitor 32 may be changedby changing the para number of the transistor 35 b of the voltagefollower 35, the charging current of the timer capacitor 32 may bechanged by changing the para number of the transistors 37 a and 37 b ofthe current mirror circuit 37, or the charging current of the timercapacitor 32 may be changed by changing the division ratio of the inputvoltage division circuit 34.

Furthermore, although the frequency of the reference clock Cref of theadjustment section 60 is the same as the frequency of the switchingcontrol signal Ssw in this embodiment, the ratio between the frequencyof the reference clock Cref and the frequency of the switching controlsignal Ssw may also be N:M (where M and N are natural numbers). Here,the adjustment section 60 adjusts the predetermined ON width of the ONpulse of the switching control signal so that the ratio between thecount value of the switching control signal Ssw and the count value ofthe reference clock Cref is M:N. In particular, the frequency of thereference clock Cref is preferably lower than the frequency of theswitching control signal Ssw. The current consumption can accordingly bereduced.

Furthermore, although the first counter 61 counts only the ON pulses ofthe switching control signal Ssw in this embodiment, the first counter61 may also count at least either one of the ON pulses and OFF pulses ofthe switching control signal Ssw.

In addition, although the output voltage Vout is input to the negativeinput terminal of the second comparator in this embodiment, a referencevoltage may also be input to the negative input terminal of the secondcomparator.

Furthermore, although a switching-type voltage conversion section whichemploys a diode rectification system is illustrated as the voltageconversion section in this embodiment, the voltage conversion sectionmay also be a synchronous rectification system switching-type voltageconversion section which employs a switching element instead of thediode 12. In this case, the adjustment stoppage section stops theswitching element instead of the diode 12 on the basis of an inverteddetection signal.

Although an n-type MOSFET is employed as the switching element 11 of thevoltage conversion section 100 in this embodiment, a p-type MOSFET mayalso be employed. In addition, various transistors such as a FET or abipolar transistor can be applied to the switching element or transistorof this embodiment.

1. A comparator-system DC-DC converter, comprising: a voltage conversionsection which has an input terminal to which an input voltage is inputand a pair of output terminals, and further has a switching elementhaving one current terminal connected to the input terminal, an inductorhaving one end connected to the other current terminal of the switchingelement and another end connected to one of the pair of outputterminals, and a smoothing capacitor connected between the pair ofoutput terminals, the voltage conversion section generating an outputvoltage which is obtained by voltage-converting the input voltage,across the pair of output terminals by controlling the switching elementin accordance with a control signal which is a pulse signal; and acontrol unit which generates the control signal for stabilizing theoutput voltage of the voltage conversion section, wherein the controlunit comprises: a comparator section which compares the output voltageof the voltage conversion section with a reference voltage anddetermines a predetermined ON width of an ON pulse of the control signalor a predetermined OFF width of the OFF pulse of the control signal inaccordance with the comparison result; and frequency control means whichcompares the control signal with a reference clock and adjusts thepredetermined ON width of the ON pulse or the predetermined OFF width ofthe OFF pulse in accordance with the comparison result so that therepetition frequency of the control signal is constant, and wherein thefrequency control means comprises an adjustment stoppage section whichdetects a state where an output current which flows in a direction fromthe switching element of the voltage conversion section toward theinductor is 0 A or a state where the output current is going to be 0 Aand generates an adjustment stoppage signal which stops the processingof the frequency control means to adjust the predetermined ON width orthe predetermined OFF width.
 2. The comparator-system DC-DC converteraccording to claim 1, wherein the comparator section comprises: a firstcomparator which detects that the output voltage of the voltageconversion section is smaller than the reference voltage and determinesthe detection time point as the start time point of the ON pulse or theOFF pulse; and a second comparator which detects that a predeterminedtime has elapsed since the start time point of the ON pulse or the OFFpulse and determines the detection time point as the end time point ofthe ON pulse or the OFF pulse, and wherein the frequency control meanscomprises an adjustment section which adjusts the predetermined ON widthor the predetermined OFF width by adjusting the predetermined time. 3.The comparator-system DC-DC converter according to claim 1, wherein thefrequency control means comprises a reference clock generation sectionwhich generates the reference clock; and in cases where the frequencycontrol means acquires the adjustment stoppage signal from theadjustment stoppage section, the reference clock generation sectiontemporarily stops the generation of the reference clock and stops theprocessing to adjust the predetermined ON width or the predetermined OFFwidth.
 4. The comparator-system DC-DC converter according to claim 1,wherein, in cases where the frequency control means acquires theadjustment stoppage signal from the adjustment stoppage section, thefrequency control means stops the comparison between the control signaland the reference clock and stops the processing to adjust thepredetermined ON width or the predetermined OFF width.
 5. Thecomparator-system DC-DC converter according to claim 1, wherein, incases where the frequency control means acquires the adjustment stoppagesignal from the adjustment stoppage section, the frequency control meansstops the processing to adjust the predetermined ON width or thepredetermined OFF width by substituting the result of comparing thecontrol signal with the reference clock, with a predetermined fixedvalue which is determined beforehand.